MOTOROLA Manuals

The MC10EL/100EL07 is a 2-input XOR/XNOR gate that is functionally equivalent to the E107 with higher performance capabilities. With propagation delays and output transition times significantly faster than the E107 the EL07 is ideally suited for those applications which require the ultimate in AC performance.

The MC10EL/100EL07 is a 2-input XOR/XNOR gate with higher performance capabilities. With propagation delays and output transition times significantly faster than the E107 the EL07 is ideally suited for those applications which require the ultimate in AC performance.

MC10EL/100EL07 is a 2-input XOR/XNOR gate with higher performance capabilities. With propagation delays and output transition times significantly faster than the E107 the EL07 is ideally suited for those applications which require the ultimate in AC performance.

The MC10EL/100EL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the EL11 is ideally suited for those applications which require the ultimate in AC performance. The differential inputs of the EL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to VEE) the Q outputs will go LOW.

MC10EL/100EL11 is a differential 1:2 fanout buffer with 265ps propagation delay and 5ps skew between outputs.

The MC10EL/100EL12 is a low impedance drive buffer. With two pairs of OR/NOR outputs the device is ideally suited for high drive applications such as memory addressing. The device is a function equivalent to the E112 device with higher performance capabilities. With propagation delays significantly faster than the E112 the EL12 is ideally suited for those applications which require the ultimate in AC performance.

The MC10EL/100EL12 is a low impedance drive buffer with two pairs of OR/NOR outputs, ideally suited for high drive applications such as memory addressing. The device is a function equivalent to the E112 device with higher performance capabilities. With propagation delays significantly faster than the E112, the EL12 is ideally suited for applications that require the ultimate in AC performance. It features a propagation delay of 290ps, dual outputs for 25Ω drive applications, 75kΩ internal input pulldown resistors, and >1000V ESD protection.

The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer from Motorola. The MC100EL13 is pin and functionally equivalent to the MC100LVEL13 but is specified for operation at the standard 100E ECL voltage supply. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW.

The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer from Motorola. The MC100EL13 is pin and functionally equivalent to the MC100LVEL13 but is specified for operation at the standard 100E ECL voltage supply. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE, The D input will bias around VCC/2 and the Q output will go LOW. • Differential Inputs and Outputs • 20-Lead SOIC Packaging • 500ps Typical Propagation Delays • 50ps Output-Output Skews • Supports Both Standard and Low Voltage 100K ECL • >2000V ESD Protection.

MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL14 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated outputs are latched to the LOW state.

MC100LVEL/100EL14 is a low-skew 1:5 clock distribution chip designed specifically for low-skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14, but is designed to operate in ECL or PECL mode for a voltage supply range of –3.0V to –3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL14 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated outputs must be clocked on the rising edge of the clock.

The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. • 50ps Output-to-Output Skew • Synchronous Enable/Disable • Multiplexed Clock Input • 75kΩ Internal

The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.

The MC100EL1648 is a low power voltage controlled oscillator that can be used in many applications requiring a fixed frequency clock. It is based on the VCO circuit topology of the MC1648 and is realized using Motorola's MOSAIC III advanced bipolar process technology, allowing it to operate at a higher frequency while consuming less current compared to the MC1648. The MC100EL1648 features ECL output circuitry with an on-chip termination resistor, enabling direct AC-coupling of the output signal into a transmission line.

The MC10E416/100E416 is a 5-bit differential line receiving device. The 2.0GHz of bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. A VBB pin is available to AC couple an input signal to the device. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications. The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device.