Micrel manuals, page 7
MICREL PROGRAMMABLE DELAY CHIP ClockWorks SY10E195 SY100E195 handbook
The SY10E195/100E195 are programmable delay chips (PDCs) designed primarily for clock de-skewing and timing adjustment. They provide variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in the logic diagram. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on-chip by a high signal on the latch enable (LEN) control. If the LEN signal is either LOW or left floating, then the latch is transparent. Because the delay programmability of the E195 is achieved by purely differential ECL gate delays, the device will operate at frequencies of >1GHz, while maintaining high push-pull outputs, suitable for a wide variety of circuit applications.
MICREL ERROR DETECTION/ CORRECTION CIRCUIT SY10E193 SY100E193 handbook
SY10/100E193 is an error detection and correction (EDAC) circuit designed for use in new, high-performance ECL systems. It generates hamming parity codes on an 8-bit word and has various features such as expandability, full compatibility, and internal input pulldown resistors.
MICREL 9-BIT LATCH WITH PARITY SY10E175 SY100E175 handbook
The SY10/100E175 are 9-bit latches. They also feature a tenth latched output (ODDPAR) which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity) and using ODDPAR as the byte parity output. The LEN pin latches the data when asserted with a logical high and makes the latch transparent when placed at a logic low level.
Micrel 3-BIT 4:1 MULTIPLEXER SY10E171 SY100E171 Manual
The SY10/100E171 is a 3-bit 4:1 multiplexer designed for use in new, high-performance ECL systems. It features differential outputs, split select architecture, and full compatibility with industry standard 10KH, 100K ECL levels.
MICREL SY10E166 SY100E166 handbook
Micrel 16:1 MULTIPLEXER SY10E164 SY100E164 Manual
SY10/100E164 is a 16:1 multiplexer with a differential output. The select inputs (SEL0,1,2,3) control which one of the sixteen data inputs (A0–A15) is propagated to the output. Special attention to the design layout results in a typical skew between the 16 inputs of only 50ps.
Micrel 2-BIT 8:1 MULTIPLEXER SY10E163 SY100E163 Manual
The SY10E163/100E163 are two 8:1 multiplexers designed for use in new, high-performance ECL systems. The E163 has differential outputs and common select inputs. The select inputs (SEL0, SEL1, SEL2) determine which one of the eight data inputs (A0–A7, B0–B7) is propagated to the output.
Micrel 12-BIT PARITY GENERATOR/CHECKER SY10E160 SY100E160 Manual
The SY10/100E160 are high-speed, 12-bit parity generator/checkers with differential outputs, for use in new, high-performance ECL systems. The output Q takes on a logic HIGH value only when an odd number of inputs are at a logic HIGH. A logic HIGH on the enable input (EN) forces the output Q to a logic LOW. An additional feature of the E160 is the output register. Two multiplexers and their associated signals control the register input by providing the option of holding present data, loading the new parity data or shifting external data in. To hold the present data, the Hold signal (HOLD) must be at a logic LOW level. If the HOLD signal is at a logic HIGH, the data present at the Q output is passed through the first multiplexer. Taking the Shift signal (SHIFT) to a logic HIGH will shift the data at the S-IN pin into the output register. If the SHIFT signal is at a logic LOW, the output of the first multiplexer is then passed through to the register. The register itself is clocked on the rising edge of CLK1 or CLK2 (or both).
Micrel 5-BIT 2:1 MULTIPLEXER SY10E158 SY100E158 Manual
SY10/100E158 5-BIT 2:1 MULTIPLEXER is a high-performance ECL system multiplexer with differential outputs, fully compatible with industry standard 10KH, 100K ECL levels, with built-in 75KΩ input pull-down resistors, compatible with Motorola MC10E/100E158, available in a 28-pin PLCC package.
MICREL SY10E158 SY100E158 handbook
The SY10/100E158 is a 5-bit 2:1 multiplexer with differential outputs, designed for use in new, high-performance ECL systems. The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed through.
MICREL SY10E157 SY100E157 MULTIPLEXER handbook
The SY10E157 is a quad 2:1 multiplexer with differential outputs manufactured by Micrel. It features individual select controls and is suitable for random logic designs.
MICREL SY10E156 SY100E156 MUX-LATCH handbook
The SY10/100E156 is a 3-bit 4:1 MUX-Latch designed for use in new, high-performance ECL systems. It features differential outputs, asynchronous Master Reset, dual latch enables, fully compatible with industry standard 10KH, 100K ECL levels, internal 75KΩ input pulldown resistors, and is available in a 28-pin PLCC package.
MICREL SY10E155 SY100E155 MUX-LATCH handbook
SY10/100E155 is a 6-bit 2:1 multiplexer with single-ended outputs, designed for use in new, high-performance ECL systems.
MICREL SY10E154 SY100E154 MUX-LATCH handbook
The SY10/100E154 is a 5-bit 2:1 multiplexer followed by latches with differential outputs, designed for use in new, high-performance ECL systems. It features asynchronous master reset, dual latch-enables, and is fully compatible with industry standard 10KH, 100K ECL levels. The product is available in a 28-pin PLCC package.
MICREL SY10E151 SY100E151 FINAL handbook
The document introduces a product called SY10/100E151. It is a high-speed, edge-triggered 6-bit D-type register with differential outputs. The product features include: toggle frequency of 1100MHz, VEE range of -4.2V to -5.46V, asynchronous master reset, dual clocks, full compatibility with industry standard 10KH, 100K ECL levels, internal 75KΩ input pulldown resistors, full compatibility with Motorola MC10E/100E151, and available in 28-pin PLCC package.