Micrel Manuals

The SY10/100E150 is a 6-bit D latch with differential outputs designed for use in new, high-performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW.

The document describes the features and characteristics of the SY10/100E143 high-speed 9-bit hold register, designed for use in new, high-performance ECL systems. It features parallel input data interface, mode selection, clock inputs, master reset function, etc. The product is suitable for high-speed registers, pipeline registers, synchronous operation, and byte-wide parity applications.

This document describes a high-speed 9-bit shift register designed for use in new, high-performance ECL systems. It features both parallel and serial input capabilities and is suitable for applications such as diagnostic scan registers, parallel-to-serial conversions, and byte-wide parity.

SY10/100E141 is an 8-bit full-function shift register designed for use in new, high-performance ECL systems. E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D0–D7 accept parallel input data, while DL/DR accept serial input data for left/right shifting. The two select pins, SEL0 and SEL1 permit four modes of operation: Load, Hold, Shift Left and Shift Right, as shown in the Truth Table. Input data is clocked into the register on the rising clock edge after meeting the minimum set-up time. A logic HIGH on the Master Reset (MR) pin asynchronously resets all the registers to zero.

SY10E137, SY100E137 are very high speed binary ripple counters from Micrel. The device has a minimum clock frequency of 1.8GHz and can be used in various applications.

This document describes the features and characteristics of the NTB23N03R power MOSFET, which is designed for low voltage, high-speed switching applications in power supplies, converters, power motor controls, and bridge circuits.

The SY10/100E137 are very high speed binary ripple counters, capable of operating at very high frequencies while maintaining a moderate power dissipation level. The products have various features and characteristics, including a minimum count frequency of 1.8GHz, an extended -4.2V to -5.5V VEE range, synchronous and asynchronous enable pins, differential clock input and data output pins, etc.

SY10/100E136 are 6-bit synchronous, presettable, cascadable universal counters. These devices generate a look-ahead-carry output and accept a look-ahead-carry input. These two features allow for the cascading of multiple E136s for wider bit width counters that operate at very nearly the same frequency as the stand-alone counter. When the E136 reaches terminal count before, the CLOUT output will pulse LOW for one clock cycle one count. When the counter reaches terminal count, the COUT output will pulse LOW for one clock cycle. For more information on utilizing the look-ahead-carry features of the device, please refer to the applications section of this data sheet. The differential COUT output facilitates the E136's use in programmable divider and self-stopping counter applications. Unlike the H136 and other similar universal counter designs, the E136 carry-out and look-ahead-carry-out signals are registered on chip. This design alleviates the error caused by the carry delay.

The SY10/100E131 are high-speed quad master slave D-type flip-flops with differential outputs designed for use in new, high-performance ECL systems. The flip-flops may be individually clocked by holding CC (Common Clock) at a logic LOW and then using the four individual CE (Clock Enable CE0–CE3) inputs to accomplish such clocking. Asynchronous set and reset controls are provided.

The SY10/100E122 are 9-bit buffers designed for use in new, high-performance ECL systems. The E122 provides nine non-inverting buffers.

The SY10/100E116 are quint differential line receivers designed for use in new, high-performance ECL systems. These devices have emitter-follower outputs and an internally generated reference supply (VBB) for single-ended reception.

SY10E112 is a high-performance ECL driver from Micrel. The device has a maximum propagation delay of 600ps, a VEE range of -4.2V to -5.5V, is compatible with industry standard 10KH and 100K I/O levels, has internal 75KΩ input pull-down resistors, and is compatible with Motorola MC10E/100E112. The device is available in a 28-pin PLCC package.

The SY10/100E111 is a low-skew 1-to-9 differential driver designed for clock distribution in new, high-performance ECL systems. They accept one differential or single-ended input, with VBB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of “basic” processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used.

This document describes the features and characteristics of the SY10/100E111A/L 1:9 differential clock driver, which supports 5V and 3.3V power supply options and offers low jitter and low voltage operation.

The SY10/100E111AE/LE are low skew 1-to-9 differential drivers designed for clock distribution in mind. The SY10/ 100E111AE/LE's function and performance are similar to the popular SY10/100E111, with the improvement of lower jitter and the added feature of low voltage operation. It accepts one signal input, which can be either differential or single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The E111AE/LE is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within a device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot. The net result is a dependable, guaranteed low skew device. To ensure that the tight skew specification is met it is necessary that both sides of the differential output a