MAXIM Manuals

The MAX9326 low-skew, 1:9 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max)

MAX9322 is a low-jitter 1:15 differential clock driver that reproduces or divides one of two differential input clocks at 15 differential outputs. An input multiplexer selects from one of two input clocks with input switching frequency in excess of 1.0GHz. The 15 outputs are arranged in four banks with 2, 3, 4, and 6 outputs, respectively. Each output bank is individually programmable to provide a divide-by-1 or divide-by-2 frequency function. The MAX9322 operates in LVPECL systems with a +2.375V to +3.8V supply or in LVECL systems with a -2.375V to -3.8V supply. A VBB reference output provides compatibility with single-ended clock input signals and a master reset input provides a simultaneous reset on all outputs. The MAX9322 is available in 52-pin TQFP and 68-pin QFN packages and is specified for operation over -40°C to +85°C. For 1:10 clock drivers, refer to the MAX9311/MAX9313 data sheet. For 1:5 clock drivers, refer to the MAX9316 data sheet. Applications include precision clock distribution, low-jitter data repeaters, central-office backplane clock distribution, DSLAM backplane, base stations and ATE.

The MAX9325 low-skew, 2:8 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device selects one of the two differential HSTL or LVECL/LVPECL inputs and repeats them at eight differential outputs. Outputs are compati- ble with LVECL and LVPECL, and can directly drive 50Ω terminated transmission lines. The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output volt- age VBB. All inputs have internal pulldown resistors to VEE. The internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at VEE. The MAX9325 operates over a 2.375V to 3.8V supply range for interfacing to differential HSTL and LVPECL signals. This allows high-performance clock or data dis- tribution in systems with a nominal +2.5V or +3.3V sup- ply. For LVECL operation, the device operates with a -2.375V to -3.8V supply. The MAX9325 is offered in 28-lead PLCC and space- saving 28-lead QFN packages. The MAX9325 is speci- fied for operation from -40°C to +85°C. Applications Precision Clock Distribution Low-Jitter Data Repeaters Features ♦ 50ps (max) Output-to-Output Skew ♦ 1.5psRMS (max) Random Jitter ♦ Guaranteed 300mV Differential Output at 700MHz ♦ +2.375V to +3.8V Supplies for Differ

The MAX9323 is a low-skew, low-jitter clock and data driver that distributes one of two single-ended LVCMOS inputs to four differential LVPECL outputs. The device operates from 3.0V to 3.6V and consumes only 25mA (max) of supply current, making it ideal for 3.3V systems. It features low 150ps part-to-part skew, low 11ps output-to-output skew, and low 1.7ps RMS jitter, making it suitable for clock and data distribution across a backplane or board. The MAX9323 is pin compatible with the ICS8535-01 and is available in space-saving TSSOP and thin QFN packages. It is suitable for precision clock distribution, low-jitter data repeaters, data and clock drivers, and buffers in various applications.

MAX9324 is a low-skew, low-jitter, clock and data driver that distributes a differential LVPECL input to four differential LVPECL outputs and one single-ended LVCMOS output. When the differential inputs are equal to GND or are left open, all outputs default to logic low. The MAX9324 operates from 3.0V to 3.6V, making it ideal for 3.3V systems, and consumes only 25mA (max) of supply current. The MAX9324 features low 150ps (max) part-to-part skew, low 15ps output-to-output skew, and low 1.7ps RMS jitter, making the device ideal for clock and data distribution across a backplane or board. CLK_EN and SEOUT_Z control the status of the various outputs. Asserting CLK_EN low configures the differential (Q_, Q_) outputs to a differential low condition and SEOUT to a single-ended logic-low state. CLK_EN operation is synchronous with the CLK_ inputs. A logic high on SEOUT_Z places SEOUT in a high-impedance state. SEOUT_Z is asynchronous with the CLK (CLK) inputs. The MAX9324 is available in space-saving 20-pin TSSOP and ultra-small 20-pin 4mm × 4mm thin QFN packages and operates over the extended (-40°C to +85°C) temperature range. Applications Precision Clock Distribution Low-Jitter Data Repeater Data and Clock Driver and Buffer Central-Office Backplane Clock Distribution DSLAM Backplane Base Station ATE Features o 15ps Differential Output-to-Output Skew o 1.7psRMS Added Random Jitter o 150ps (max) Part-to-Part Skew o 450ps Propagation Delay o Synchronous Output Enable/Disable

The MAX9174/MAX9175 are 670MHz, low-jitter, low-skew 1:2 splitters ideal for protection switching, loop- back, and clock and signal distribution. The devices feature ultra-low 1.0ps(RMS) random jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing errors. The MAX9174 has a fail-safe LVDS input and LVDS out- puts. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX9174 features a fail-safe circuit that dri- ves the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX9175 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9174/MAX9175 are available in 10-pin µMAX and 10-lead thin QFN with exposed pad pack- ages, and operate from a single +3.3V supply over the -40°C to +85°C temperature range.

The MAX9169/MAX9170 low-jitter, low-voltage differential signaling LVDS/LVTTL-to-LVDS repeaters are ideal for applications that require high-speed data or clock distribution while minimizing power, space, and noise. The devices accept a single LVDS (MAX9169) or LVTTL (MAX9170) input and repeat the input at four LVDS outputs. Each differential output drives 100Ω, allowing point-to-point distribution of signals on transmission lines with 100Ω termination at the receiver input. The MAX9169 and MAX9170 are pin compatible with the SN65LVDS104 and SN65LVDS105, respectively, and offer improved pulse-skew performance. Ultra-low 150ps (max) pulse skew and 200psP-P (max) added deterministic jitter ensure reliable communication in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery or serializers and deserializers. The high-speed switching performance guarantees 630Mbps data rate and less than 120ps channel-to-channel skew over the 3.0V to 3.6V operating supply range. Supply current is 30mA (max) for the MAX9169, and 25mA (max) for the MAX9170. LVDS inputs and outputs conform to the ANSI EIA/TIA-644 standard. A fail-safe feature on the MAX9169 sets the output high when the input is undriven and open, terminated, or shorted. The MAX9169/MAX9170 are offered in 16-pin TSSOP and SO packages, and operate over an extended -40°C to +85°C temperature range. Refer to the MAX9130 data sheet for an LVDS lin

The MAX3681 deserializer is a high-performance device that is ideal for converting 622Mbps serial data to 4-bit-wide, 155Mbps parallel data in ATM and SDH/SONET applications. It operates from a single +3.3V supply and accepts PECL serial clock and data inputs. It delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. The device also provides an LVDS synchronization input that enables data realignment and reframing. The MAX3681 is available in the extended-industrial temperature range (-40°C to +85°C) and comes in a 24-pin SSOP package.

The MAX3690 serializer is ideal for converting 8-bit-wide, 77Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts TTL clock and data inputs, and delivers a 3.3V differential PECL serial-data output. A fully integrated PLL synthesizes an internal 622MHz serial clock from a low-speed crystal reference clock (77.76MHz, 51.84MHz, or 38.88MHz). The MAX3690 is available in the extended-industrial temperature range (-40°C to +85°C) in a 32-pin TQFP package.

The MAX3693 serializer is ideal for converting 4-bit- wide, 155Mbps parallel data to 622Mbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers a 3.3V PECL serial-data output. A fully integrated PLL synthesizes an internal 622Mbps serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference clock. The MAX3693 is available in the extended temperature range (-40°C to +85°C), in a 32-pin TQFP package.

The MAX3890 serializer is an ideal device for converting 16-bit-wide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. It operates from a single +3.3V supply and accepts low-voltage differential-signal (LVDS) clock and data inputs to interface with high-speed digital circuitry, delivering positive-referenced emitter-coupled logic (PECL) serial data and clock outputs. The device features a fully integrated phase-locked loop (PLL) that synthesizes an internal 2.5GHz serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference clock. A loopback data output is provided for system diagnostic testing. The MAX3890 is available in a 64-pin TQFP exposed-pad (EP) package, suitable for extended temperature range (-40°C to +85°C) applications.

The MAX3880 is an integrated deserializer with clock recovery from Texas Instruments, which converts 2.488Gbps serial data to 16-bit-wide, 155Mbps parallel data for SDH/SONET applications. The device operates at a single +3.3V supply and accepts high-speed serial-data inputs and delivers low- voltage differential-signal (LVDS) parallel clock and data outputs for interfacing with digital circuitry. The MAX3880 includes a low-power clock recovery and data retiming function for 2.488Gbps applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input; the signal is then retimed by the recovered clock. The MAX3880’s jitter performance exceeds all SDH/SONET specifications. An additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTL-compatible loss-of-lock (LOL) monitor and LVDS synchronization inputs that enable data realignment and reframing. The MAX3880 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed pad) package.

MAX3885 is a high-performance, low-power 2.488Gbps serial data to 16-bit 155Mbps parallel data deserializer from Maxim that operates from a single +3.3V supply and accepts PECL serial clock and data inputs, and delivers LVDS clock and data outputs for interfacing with high-speed digital circuitry.

The MAX3892 is an ideal 4-bit-wide, 622Mbps parallel data to 2.5Gbps serial data serializer for DWDM and SONET/SDH applications.

The MAX3680/MAX3680A deserializer is ideal for converting 622Mbps serial data to 8-bit-wide, 77Mbps parallel data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers TTL clock and data outputs. The MAX3680 also provides a TTL synchronization input that enables data realignment and reframing. The MAX3680/MAX3680A is available in the extended-industrial temperature range (-40°C to +85°C), in a 28-pin SSOP package.