MAXIM Manuals

The MAX3840 is a MAXIM high-performance dual 2×2 asynchronous crosspoint switch for SDH/SONET DWDM and other high-bandwidth data switching applications, suitable for OC-48 systems with forward error correction. It features high bandwidth, fully differential signal path, which minimizes jitter accumulation, crosstalk and signal skew. Each 2×2 crosspoint switch can fan out and/or multiplex up to 2.7Gbps data and 2.7GHz clock signals. All inputs and outputs are compatible with current mode logic (CML) and can be easily adapted to interface with an AC-coupled LVPECL signal. When not used, each CML output stage can be powered down with an enable control to conserve power. Typical power consumption is 460mW with all outputs enabled. The MAX3840 is compatible with the MAX3876 2.5Gbps clock and data recovery (CDR) circuit. The MAX3840 is available in a 32-pin exposed-pad QFN package (5mm×5mm footprint) and operates from a +3.3V supply over a temperature range of -40°C to +85°C.

The MAX9152 is a 2 x 2 crosspoint switch designed for applications requiring high speed, low power, and low-noise signal distribution. This device includes two LVDS/LVPECL inputs, two LVDS outputs, and two logic inputs that set the internal connections between differ- ential inputs and outputs. The MAX9152 can be programmed to connect any input to either or both outputs, allowing it to be used in the following configurations: 2 ✕ 2 crosspoint switch, 2:1 mux, 1:2 demux, 1:2 splitter, or dual repeater. This flexi- bility makes the MAX9152 ideal for protection switching in fault-tolerant systems, loopback switching for diag- nostics, fanout buffering for clock/data distribution, and signal regeneration for communication over extended distances. Ultra-low 120psPK-PK (max) PRBS jitter ensures reliable communications in high-speed links that are highly sen- sitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializ- ers. The high-speed switching performance guarantees an 800Mbps data rate and less than 50ps (max) skew between channels. LVDS inputs and outputs are compatible with the TIA/EIA-644 LVDS standard. The LVDS inputs are designed to also accept LVPECL signals directly, and PECL signals with an attenuation network. The LVDS outputs are designed to drive 75Ω or 100Ω loads, and feature a selectable differential output resistance to minimize reflections. The MAX9152 is available in 16-pin TSSOP and SO packag

The MAX3783 is a dual serial multiplexer (mux) and buffer with selectable line-side loopback for system interconnect and serial backplane applications up to 2.7Gbps. Each independent channel consists of a transmitter with fanout of two and a receiver with a 2:1 input mux. Selectable loopback paths support system testing. Operating from a single 3.3V supply, this device has current-mode logic (CML) inputs and outputs, which can be AC-coupled for PECL compatibility, if desired. The IC is packaged in a compact 48-pin TQFP-EP package with exposed pad. Typical power consumption is 1.12W. Applications include 2.7Gbps Serial Communications System Interconnect, Serial Backplane Fail-Over and Protection Switching.

The MAX1134/MAX1135 are 150ksps, 16-bit ADCs. These serially interfaced ADCs connect directly to SPI™, QSPI™, and MICROWIRE™ devices without external logic. They combine an input scaling network, internal track/hold (T/H), clock, and three general-purpose digital output pins (for external multiplexer or PGA control) in a 20-pin SSOP package. The excellent dynamic performance (THD ≥ 90dB), high speed (150ksps in bipolar mode), and low power (8.0mA) of these ADCs make them ideal for applications such as industrial process control, instrumentation, and medical applications. The MAX1134 accepts input signals of 0 to +6V (unipo- lar) or ±6V (bipolar), while the MAX1135 accepts input signals of 0 to +2.048V (unipolar) or ±2.048V (bipolar). Operating from a single 3.135V to 3.465V analog and digital supply, power-down modes reduce current con- sumption to 0.15mA at 10ksps and further reduce sup- ply current to less than 20µA at slower data rates. A serial strobe output (SSTRB) allows direct connection to the TMS320 family digital-signal processors. The MAX1134/MAX1135 user can select either the internal clock or an external serial-interface clock for the ADC to perform analog-to-digital conversions. The MAX1134/MAX1135 feature internal calibration cir- cuitry to correct linearity and offset errors. On-demand calibration allows the user to optimize performance. Three user-programmable logic outputs are provided for the control of an 8-channel mux or PGA.

The MAX9380 is a high-precision clock distributor that uses a 2:1 multiplexer with single-ended inputs and differential outputs. It has low part-to-part skew and propagation delay. It is selected by a single select input, and the select and data inputs have internal pull-down resistors that ensure a low default state if they are left open.

MAX9384 is a dual 2:1 differential multiplexer from MAXIM. It features extremely low propagation delay (560ps max) and output-to-output skew (40ps max). It is ideal for clock and data multiplexing applications. The two 2:1 multiplexers are controlled individually or simultaneously through multiplexer select inputs COM_SEL, SEL0 and SEL1. The multiplexer select inputs are compatible with ECL/PECL logic and referenced to on-chip outputs VBB0 and VBB1, nominally VCC-1.33V. The differential inputs D, D can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip supply output VBB as a reference voltage. All the differential inputs have bias and clamp circuits that force the outputs to a low default when the inputs are left open or at VEE. The single-ended multiplexer select inputs have pulldowns to VEE, providing low default inputs when the select inputs are left open. The device operates with a wide supply range (VCC-VEE) of +3.0V to +5.5V for PECL or -3.0V to -5.5V for ECL and is pin compatible with the MC100LVEL56 and MC100EL56. The MAX9384 is offered in a 20-pin wide SO package and is specified for operation from -40°C to +85°C.

This datasheet details the features of MAX9386/MAX9387/MAX9388, including application scenarios, pin definitions, working conditions, and package dimensions.

The MAX9176/MAX9177 are 670MHz, low-jitter, low-skew 2:1 multiplexers ideal for protection switching, loopback, and clock distribution. The devices feature ultra-low 68ps peak-to-peak deterministic jitter that ensures reliable operation in high-speed links that are highly sensitive to timing errors. The MAX9176 has fail-safe LVDS inputs and an LVDS output. The MAX9177 has “anything” differential inputs (CML/LVDS/LVPECL) and an LVDS output. The output can be put into high impedance using the power-down input. The MAX9176 features fail-safe circuits that drive the output high when a selected input is open, undriven and shorted, or undriven and terminated. The MAX9177 has bias circuits that force the output high when a selected input is open. The mux select and power-down inputs are compatible with standard LVTTL/ LVCMOS logic. The select and power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9176/ MAX9177 are available in 10-pin µMAX and 10-lead thin QFN packages, and operate from a single 3.3V supply over the -40°C to +85°C temperature range.

The MAX9389 is a fully differential, high-speed, low-jitter, 8-to-1 ECL/PECL multiplexer (mux) with dual output buffers. The device is designed for clock and data distribution applications, and features extremely low propagation delay and output-to-output skew. It has three single-ended select inputs that are compatible with ECL/PECL logic. The differential inputs can be configured to accept a single-ended signal. The MAX9389 operates with a wide supply range and is suitable for high-speed telecom and datacom applications.

The MAX9390/MAX9391 dual 2 x 2 crosspoint switches perform high-speed, low-power, and low-noise signal distribution. The MAX9390/MAX9391 multiplex one of two differential input pairs to either or both low-voltage differential signaling (LVDS) outputs for each channel. Independent enable inputs turn on or turn off each differential output pair. Four LVCMOS/LVTTL logic inputs (two per channel) control the internal connections between inputs and outputs. This flexibility allows for the following configurations: 2 x 2 crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater. This makes the MAX9390/MAX9391 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9390 provides high-level input fail-safe detection for LVDS, HSTL, and other GND-referenced differential inputs. The MAX9391 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs. Ultra-low 82ps(P-P) (max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.5 to 15.8 Gb/s of bandwidth, with eye patterns sufficient to ensure high reliability.

The MAX9392/MAX9393 dual 2 x 2 crosspoint switches perform high-speed, low-power, and low-noise signal distribution. The MAX9392/MAX9393 multiplex one of two differential input pairs to either or both low-voltage differential signaling (LVDS) outputs for each channel. Independent enable inputs turn on or turn off each differential output pair. Four LVCMOS/LVTTL logic inputs (two per channel) control the internal connections between inputs and outputs. This flexibility allows for the following configurations: 2 x 2 crosspoint switch, 2:1 mux, 1:2 splitter, or dual repeater. This makes the MAX9392/MAX9393 ideal for protection switching in fault-tolerant systems, loopback switching for diagnostics, fanout buffering for clock/data distribution, and signal regeneration. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9392 provides high-level input fail-safe detection for LVDS, HSTL, and other GND-referenced differential inputs. The MAX9393 provides low-level input fail-safe detection for LVPECL, CML, and other VCC-referenced differential inputs. Ultra-low 98ps(P-P) (max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees 1.5 Gbps communication rate.

MAX3841 is a 12.5Gbps 2x2 crosspoint switch IC for high-speed serial data loopback, redundancy, and switching applications. The device features fully differential signal paths and Maxim's second-generation SiGe technology to provide optimum signal integrity, minimizing jitter, crosstalk, and signal skew. MAX3841 is ideal for OC-192 and 10GbE optical module, line card, switch fabric, and similar applications. MAX3841 has a 150mVpp minimum differential input sensitivity and 500mVpp nominal differential output swing. Unused outputs can be individually powered down to conserve power. In addition to functioning as a 2x2 switch, MAX3841 can be configured as a 2:1 multiplexer, 1:2 buffer, or dual 1:1 buffer. MAX3841 is available in a 4mm x 4mm 24-pin thin QFN package and consumes only 215mW with both outputs enabled.

The MAX9394/MAX9395 consist of a 2:1 multiplexer and a 1:2 demultiplexer with loopback. The multiplexer section (channel B) accepts two low-voltage differential signaling (LVDS) inputs and generates a single LVDS output. The demultiplexer section (channel A) accepts a single LVDS input and generates two parallel LVDS outputs. The MAX9394/MAX9395 feature a loopback mode that connects the input of channel A to the output of channel B and connects the selected input of channel B to the outputs of channel A. Three LVCMOS/LVTTL logic inputs control the internal connections between inputs and outputs, one for the multiplexer portion of channel B (BSEL), and the other two for loopback control of channels A and B (LB_SELA and LB_SELB). Independent enable inputs for each differential output pair provide additional flexibility. Fail-safe circuitry forces the outputs to a differential low condition for undriven inputs or when the common-mode voltage exceeds the specified range. The MAX9394 provides high-level input fail-safe detection for HSTL, LVDS, and other GND-referenced differential inputs. The MAX9395 provides low-level fail-safe detection for CML, LVPECL, and other VCC-referenced differential inputs. Ultra low 91psP-P (max) pseudorandom bit sequence (PRBS) jitter ensures reliable communications in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers.

The MAX9150 is a low-jitter, 10-port LVDS (Low-Voltage Differential Signaling) repeater designed for applications that require high-speed data or clock distribution while minimizing power, space, and noise. The device accepts a single LVDS input and repeats the signal at 10 LVDS outputs. The ultra-low 120ps (max) peak-to-peak jitter ensures reliable communication in high-speed links that are highly sensitive to timing error, especially those incorporating clock-and-data recovery, or serializers and deserializers. The high-speed switching performance guarantees a 400Mbps data rate and less than 100ps skew between channels while operating from a s

The MAX9311/MAX9313 are low-skew, 1-to-10 differential drivers designed for clock and data distribution. These devices allow selection between two inputs. The selected input is reproduced at 10 differential outputs. The differential inputs can be adapted to accept single- ended inputs by connecting the on-chip VBB supply to one input as a reference voltage. The MAX9311/MAX9313 feature low part-to-part skew (30ps) and output-to-output skew (12ps), making them ideal for clock and data distribution across a backplane or a board. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The MAX9311 features an on-chip VBB reference output of 1.425V below the positive supply voltage. The MAX9313 offers an on-chip VBB reference output of 1.32V below the positive supply voltage. Both devices are offered in space-saving, 32-pin 5mm ✕ 5mm TQFP, 5mm x 5mm QFN, and industry-standard 32-pin 7mm x 7mm LQFP packages.