This application note explains how to use the STM32F10xxx FSMC peripheral to interface with external NOR, NAND and SRAM memory devices.
The document provides a detailed guide for configuring the Flexible Static Memory Controller (FSMC) of the high‑capacity STM32F10xxx microcontrollers. It introduces the FSMC architecture, shows typical configuration examples, and describes timing calculations and hardware connections for various external memory types.
Key sections cover interfacing with 16‑bit asynchronous NOR flash, 8‑bit NAND flash, and 16‑bit SRAM, as well as ECC implementation for NAND devices, timing parameter tables, and special considerations for 100‑pin package variants. This manual is written in Chinese.
| Data bus width | 16 bits |
|---|---|
| Number of address lines | 26 |
| Maximum external memory per block | 64 MB |
| Internal AHB clock (HCLK) | 72 MHz |
The FSMC can interface with NOR flash, NAND flash, SRAM, PSRAM, PC‑Card, CF‑Card and other static memory devices.
The FSMC provides 26 address lines, allowing up to 64 MB of external memory per block.
The internal AHB clock (HCLK) runs at 72 MHz.
The FSMC includes hardware ECC that can generate 22‑32 bit codes for page sizes from 256 bytes to 8192 bytes, detecting and correcting single‑bit errors and detecting double‑bit errors.