The Hynix H5GQ2H24AFR is a 2 Gb GDDR5 SGRAM memory chip with detailed features, specifications, and operation guidelines.
This document provides a complete description of the H5GQ2H24AFR 2 Gb GDDR5 SGRAM, covering its features, functional operation, clocking, initialization, and package details. It includes tables of mode registers, command truth tables, power‑up sequences, and electrical characteristics.
The datasheet lists electrical specifications such as supply voltages, maximum data rates, IDD currents, and package dimensions for the 170‑ball BGA. It also defines signal terminology, training procedures, and scan mode operation for testing and debugging.
| Capacity | 2 Gb (2,147,483,648 bits) |
|---|---|
| Internal banks | 16 |
| Bank groups | 4 |
| Prefetch architecture | 8n (256‑bit per access) |
| Supply voltage (VDD) | 1.6 V / 1.5 V / 1.35 V ±3%×VDD |
| Maximum data rate per pin | 6.0 Gbps |
The sequence is: apply power to VDD, apply power to VDDQ, apply VREFC and VREFD, provide stable CK/CK# clocks, assert RESET# low, wait at least 200 µs, then follow the initialization steps listed in the document.
The device contains 16 internal banks.
It operates from 1.6 V, 1.5 V, or 1.35 V with a tolerance of ±3 % of VDD.
The chip can achieve up to 6.0 Gbps per pin at 1.5 V supply.