This document describes three 256M DDR SDRAM products from Hynix Semiconductor, which are ideally suited for main memory applications requiring large memory density and high bandwidth. These products feature fully synchronous operations, double data rate interface, and source synchronous data transaction.
The document describes three 256 Mb DDR SDRAM parts (HY5DU56422D(L)TP, HY5DU56822D(L)TP, HY5DU561622D(L)TP) intended for high‑density main‑memory applications. It includes a general product description, electrical specifications, pin‑out diagrams and timing tables.
Key features include a fully differential clock, SSTL‑2 compatible I/O, programmable CAS latency (1.5‑3) and burst lengths (2/4/8), on‑chip DLL alignment, and support for auto‑refresh and self‑refresh modes. The parts are offered in a 400 mil 66‑pin TSOP‑II package.
| Supply Voltage | VDD, VDDQ = 2.5 V ± 0.2 V |
|---|---|
| I/O Interface | SSTL‑2 compatible |
| Package | 400 mil 66‑pin TSOP‑II (0.65 mm pitch) |
| Organization | 64M × 4, 32M × 8, 16M × 16 |
| Programmable CAS Latency | 1.5, 2, 2.5, 3 |
| Programmable Burst Length | 2, 4, 8 (sequential or interleave) |
| Operating Frequency (Grade CL2) | 133 MHz DDR333 |
It operates at VDD and VDDQ of 2.5 V ± 0.2 V.
They are supplied in a 400 mil 66‑pin TSOP‑II package with a 0.65 mm pin pitch.
All inputs and outputs are compatible with the SSTL‑2 interface.
Yes, the devices support programmable CAS latencies of 1.5, 2, 2.5 and 3.