This Atmel application note explains how to test the TSC695 processor's EDAC trap mechanism using single and multiple error injection.
The document describes the EDAC (Error Detection And Correction) feature of the TSC695 SPARC® 32‑bit Space Processor and provides a procedure for injecting both single‑bit and multiple‑bit errors to verify trap handling. It outlines the hardware implementation, including the 32‑bit data bus, parity generation, and a 7‑bit Hamming code that together form a 40‑bit word.
Testing is performed via the processor's test control register (TSTCTR). By setting the ‘et’ bit and writing a custom check‑bit value, users can force correctable or uncorrectable errors, observe the resulting traps (0x01, 0x09, 0x16), and validate the EDAC response. Code samples illustrate how to enable testing, inject errors, and read back results.
| Data bus width | 32 bits |
|---|---|
| Total bus width | 40 bits (32 data + parity + 7‑bit checkbit) |
| EDAC detection capability | detects any double error on the 40‑bit bus |
| EDAC correction capability | corrects any single error on the 40‑bit bus |
| Error‑coding scheme | 7‑bit Hamming code |
Trap 0x01 is generated for an uncorrectable error during instruction fetch, and trap 0x09 for an uncorrectable error during data access.
The test control register (TSTCTR); setting its ‘et’ bit activates fault injection for EDAC testing.