This manual provides a comprehensive description of the Loongson 2F processor, covering its overall architecture, instruction fetch, branch prediction, and the complete register set. It also explains the functional units, pipeline stages, and the mechanisms for instruction issue and reordering.
Further sections describe the cache organization, TLB management, exception handling, floating‑point unit, CPO control, PCI configuration, DDR2 SDRAM controller, integrated I/O controller, and performance optimization techniques. Revision history and update notes are included at the end of the document. This manual is written in Chinese.
| Load Linked Address (LLAddr) register number | 17 |
|---|---|
| Watch register number | 18 |
| Performance Counter register number | 24 |
| TagLo register number | 28 |
| TagHi register number | 29 |
It is version 0.1, released in August 2007.
The processor includes multiple cache levels with defined parameters described in the cache section.
The TLB stores virtual‑to‑physical address translations and defines entry formats and refill behavior.