Loongson 3A processor user manual, introduces the overview, system configuration and control, secondary Cache, matrix transposition module, I/O interrupt, DDR2/3 SDRAM controller configuration, HyperTransport controller and other content of Loongson 3A processor.
This manual provides a detailed description of the Loongson 3A processor architecture, including core functions, cache hierarchy, and supported memory types. It also explains the HyperTransport bus interface and how to configure interrupts and peripheral controllers.
The document includes sections on EJTAG debugging, system memory allocation, and example configurations for various use cases, helping developers integrate the 3A CPU into their designs. This manual is written in Chinese.
| Supported Memory Types | DDR2/3 SDRAM |
|---|---|
| High‑Speed Bus Interface | HyperTransport |
| Interrupt Support | HT interrupt support |
It supports DDR2 and DDR3 SDRAM memory modules.
The processor uses a HyperTransport interface for high‑speed data transfer.
Interrupts are configured through HT interrupt registers and related capability registers.