This document is a user manual for Loongson 2E processor, which introduces the microarchitecture, instruction set overview, memory management, cache organization and operation, and CP0 control registers of the processor.
This manual provides a comprehensive description of the Loongson 2E processor, covering its micro‑architecture, pipeline stages, register renaming, and instruction dispatch. It also explains the virtual‑address translation, TLB operation, and the various processor modes.
Further sections describe the cache hierarchy, CP0 control registers, exception handling mechanisms, floating‑point unit, and DDR‑SDRAM controller configuration, ending with performance‑optimisation tips and appendices of new integer and floating‑point instructions. This manual is written in Chinese.
It describes the cache organization, parameters, and operation for both instruction and data caches.