Key facts
- Manuals
- 8
- Models
- 1
- Categories
- 1
- Languages
- ZH
- Last added
- 2012-03-22
Loongson models by category
Featured Loongson manuals
Loongson 3A CPU User Manual
This manual provides a detailed description of the Loongson 3A processor architecture, including core functions, cache hierarchy, and supported memory types. It also explains the HyperTransport bus interface and how to configure interrupts and peripheral controllers.
The document includes sections on EJTAG debugging, system memory allocation, and example configurations for various use cases, helping developers integrate the 3A CPU into their designs. This manual is written in Chinese.
Covers: Architecture Overview · Processor Core · Cache and Memory System · HyperTransport Interface · Interrupt Configuration · EJTAG Debugging
Loongson 2E CPU User Manual
This manual provides a comprehensive description of the Loongson 2E processor, covering its micro‑architecture, pipeline stages, register renaming, and instruction dispatch. It also explains the virtual‑address translation, TLB operation, and the various processor modes.
Further sections describe the cache hierarchy, CP0 control registers, exception handling mechanisms, floating‑point unit, and DDR‑SDRAM controller configuration, ending with performance‑optimisation tips and appendices of new integer and floating‑point instructions. This manual is written in Chinese.
Covers: Microarchitecture · Instruction Set Overview · Memory Management · Cache Organization and Operation · CP0 Control Registers · Processor Exceptions
Loongson 2F Processor Data Manual
The Loongson 2F is a 64‑bit processor compatible with the MIPS II instruction set, featuring a dynamic superscalar core, two integer units, two floating‑point units, and a load/store unit. It is fabricated in a 90 nm CMOS process and integrates a 64‑bit DDR2 memory controller, PCI/PCI‑X bus controller, local‑bus interface, interrupt controller, and video acceleration module.
The manual contains sections on chip features, interface descriptions (PCI/PCI‑X, DDR2, local bus, JTAG, clocks, power), initialization procedures, electrical and thermal characteristics, pinout and package details, and revision history. Detailed tables list signal definitions, timing parameters, and absolute maximum ratings. This manual is written in Chinese.
Covers: Chip Features · Interface Description · PCI/PCI‑X Interface · DDR2 SDRAM Controller Interface · Initialization Process · Electrical Characteristics
Loongson 2F CPU User Manual
This manual provides a comprehensive description of the Loongson 2F processor, covering its overall architecture, instruction fetch, branch prediction, and the complete register set. It also explains the functional units, pipeline stages, and the mechanisms for instruction issue and reordering.
Further sections describe the cache organization, TLB management, exception handling, floating‑point unit, CPO control, PCI configuration, DDR2 SDRAM controller, integrated I/O controller, and performance optimization techniques. Revision history and update notes are included at the end of the document. This manual is written in Chinese.
Covers: Processor Overview · Architecture and Instruction Fetch · Register Set · Cache Architecture · TLB Management · Exception Handling
Latest Loongson manuals
Loongson 2E CPU handbook
This document is the datasheet of Loongson 2E processor, which introduces the interface signal description, system bus protocol description, DDR SDRAM control interface description, chip initialization process, electrical characteristics, thermal characteristics, pin arrangement and packaging, etc.
Loongson 3A CPU User Manual
User Manual 118 pages · 908 KB · ZHTechnical user manual for the Loongson 3A CPU covering architecture, memory, HyperTransport and interrupt configuration.
Loongson 2E CPU User Manual
User Manual 128 pages · 1.6 MB · ZHThe Loongson 2E CPU User Manual details the micro‑architecture, instruction set, cache, memory management, and exception handling.
Loongson 2F Processor Data Manual
Datasheet 38 pages · 1.5 MB · ZHThe Loongson 2F processor data manual provides specifications, architecture details, pinout, and electrical characteristics for the 64‑bit MIPS‑compatible CPU.
Loongson 2F CPU User Manual
User Manual 158 pages · 1.2 MB · ZHThe Loongson 2F CPU User Manual details the architecture, registers, cache hierarchy, exception handling, and DDR2 SDRAM controller.
Loongson 2F CPU Owner's Manual
User Manual 181 pages · 2.7 MB · ZHThe Loongson 2F CPU Owner's Manual provides detailed information on architecture, registers, cache, and usage guidelines.
Loongson 2F Processor User Manual
User Manual 153 pages · 1.1 MB · ZHThe Loongson 2F Processor User Manual describes the microarchitecture, instruction set, memory management, cache, CP0 registers, and exception handling of…
Loongson 2F CPU user manual1
Which document do I need?
User Manual
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Datasheet
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in Loongson manuals
What memory types does the Loongson 3A CPU support?
It supports DDR2 and DDR3 SDRAM memory modules.
Which bus protocol is used for high‑speed communication?
The processor uses a HyperTransport interface for high‑speed data transfer.
What does the Cache section describe?
It describes the cache organization, parameters, and operation for both instruction and data caches.
What is the core clock frequency of the Loongson 2F processor?
The core clock runs at 1 GHz and can be dynamically adjusted or disabled.
How much power does the Loongson 2F consume at 1 GHz?
At 1 GHz the processor consumes less than 5 W.
What version of the Loongson 2F CPU manual is this?
It is version 0.1, released in August 2007.