Loongson 2F CPU Owner's Manual

About this manual

This manual covers the Loongson 2F processor architecture, including an overview of the CPU, instruction set, and operating modes. It describes the complete register set, TLB management, cache hierarchy, exception handling, floating‑point unit, and special instructions.

Additional sections detail the DDR2 SDRAM controller, integrated I/O controller, performance optimization tips, errata, and the revision history of the document. This manual is written in Chinese.

What's inside

• Processor Overview
• Register Set
• TLB Management
• Cache Architecture
• Exception Handling
• Floating‑Point Unit
• Special Instructions
• DDR2 SDRAM Controller
• Integrated I/O Controller

Specifications

Frequently asked questions

What is the revision date of the Loongson 2F CPU manual?

The manual was first released in August 2008, version 1.0.

Which instruction set architecture does the Loongson 2F CPU support?

It supports the MIPS64 ISA.

Where can I find the cache parameters for the Loongson 2F?

Cache parameters are described in Section 4.1.3 titled "Cache 的参数".