Loongson 2F is an improved version of Loongson 2E, with higher I/O interface bandwidth and memory access bandwidth, supports software dynamic adjustment of processor operating frequency, and is compatible with MIPS64 instruction set.
The Loongson 2F is a 64‑bit processor compatible with the MIPS II instruction set, featuring a dynamic superscalar core, two integer units, two floating‑point units, and a load/store unit. It is fabricated in a 90 nm CMOS process and integrates a 64‑bit DDR2 memory controller, PCI/PCI‑X bus controller, local‑bus interface, interrupt controller, and video acceleration module.
The manual contains sections on chip features, interface descriptions (PCI/PCI‑X, DDR2, local bus, JTAG, clocks, power), initialization procedures, electrical and thermal characteristics, pinout and package details, and revision history. Detailed tables list signal definitions, timing parameters, and absolute maximum ratings. This manual is written in Chinese.
| Core frequency | 1 GHz |
|---|---|
| Power consumption at 1 GHz | <5 W |
| DDR2 memory controller max frequency | 333 MHz |
| L1 instruction cache | 64 KB |
| L1 data cache | 64 KB |
| L2 cache | 512 KB |
| Process technology | 90 nm CMOS |
| Package type | HEFCBGA‑452 |
The core clock runs at 1 GHz and can be dynamically adjusted or disabled.
At 1 GHz the processor consumes less than 5 W.
The DDR2 memory controller supports up to 333 MHz.