This document is the datasheet of Loongson 2E processor, which introduces the interface signal description, system bus protocol description, DDR SDRAM control interface description, chip initialization process, electrical characteristics, thermal characteristics, pin arrangement and packaging, etc.
This document introduces the Loongson 2E 64‑bit MIPS III processor, describing its micro‑architecture, superscalar pipeline, cache hierarchy and integrated DDR SDRAM controller. It also covers the processor’s instruction set, branch prediction, register renaming and out‑of‑order execution features.
The manual details the system‑bus signal definitions, DDR SDRAM interface, power‑up and reset sequences, electrical limits, power consumption, thermal resistance, and pin‑out with package dimensions for the HSBGA452 package. This manual is written in Chinese.
| Maximum operating frequency | 1 GHz |
|---|---|
| Typical operating frequency | 800 MHz |
| Measured power consumption | 5–7 W |
| Transistor count | ≈47 million |
| Process technology | 90 nm CMOS |
| L2 cache size | 512 KB |
The processor can run up to a maximum frequency of 1 GHz.
Measured power consumption is between 5 and 7 watts.
The chip contains about 47 million transistors.