Philips 74HC/HCT393 Dual 4-bit Binary Ripple Counter Datasheet

This document describes the features and characteristics of the 74HC/HCT393 dual 4-bit binary ripple counter, including two 4-bit binary counters with individual clocks, the ability to divide-by any binary module up to 28 in one package, two master resets to clear each 4-bit counter individually, standard output capability, and belonging to the MSI category.


Philips 74HC/HCT393 Dual 4-bit Binary Ripple Counter Datasheet - cover page
Brand
Philips
Category
Chips
Document type
Datasheet
Language
English
Pages
7
File format
PDF
File size
51 KB
Published
20 October, 2022
Updated
27 September, 2023
Models
74HC, HCT393
MD5 checksum
1C9FCB2F8258266E5B8AEF04CDC0A820

About this manual

The 74HC/HCT393 are high-speed Si-gate CMOS devices containing two 4-bit binary counters with individual clocks. They feature separate master reset inputs for each counter and are specified in compliance with JEDEC standard no. 7A.

These devices operate as ripple counters triggered by a HIGH-to-LOW transition of the clock inputs, with outputs internally connected to provide clock inputs to succeeding stages. The counters can divide by any binary module up to 28 within a single package.

What's inside

  • Features
  • General Description
  • Quick Reference Data
  • Ordering Information
  • Pin Description
  • Count Sequence
  • DC Characteristics
  • AC Characteristics
  • Package Outlines

Specifications

Device TypeDual 4-bit binary ripple counter
TechnologyHigh-speed Si-gate CMOS
Clock InputsTwo separate clocks (1 CP and 2 CP)
Reset TypeMaster reset inputs (active HIGH)
Max Clock Frequency (HC)99 MHz
Max Clock Frequency (HCT)27 MHz
Supply Voltage Range (HC)+25 V to +6.0 V
Supply Voltage Range (HCT)+4.5 V

Frequently asked questions

How are the counters triggered?

The counters are triggered by a HIGH-to-LOW transition of the clock inputs.

What is the maximum divide-by count?

It can divide by any binary module up to 28 in one package.

Are the master resets synchronous or asynchronous?

The master resets are active-HIGH asynchronous inputs.

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