This document introduces STE10/100, a high performance PCI Fast Ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX application.
The STE10/100 is a high-performance PCI Fast Ethernet controller featuring an integrated physical layer interface for 10BASE-T and 100BASE-TX applications. Designed with advanced CMOS technology, it provides a glueless 32-bit bus master interface for the PCI bus and supports CSMA/CD protocols for Fast Ethernet.
Key features include support for IEEE 802.3x flow control, auto-negotiation for speed and duplex detection, and both half-duplex and full-duplex operation. The device includes long FIFO buffers for transmission and receiving, early interrupt mechanisms to enhance performance, and compliance with ACPI and PCI power management standards. It is available in a 128-pin QFP package.
| Package Type | 128-pin QFP |
|---|---|
| Clock Frequency | 20MHz to 33MHz |
| FIFO Size | 2k bytes |
| Interface | PCI bus interface Rev. 2.2 |
| Power Management | ACPI and PCI compliant |
The STE10/100 is available in a 128-pin QFP package.
The device supports a PCI clock frequency ranging from 0Hz to 33MHz.
Yes, it supports IEEE 802.3x flow control.