This datasheet describes the Altera® 10-Gbps Ethernet IP core which implements the IEEE 802.3 2005 and 802.1Q Ethernet standards. The 10-Gbps Ethernet IP core is highly configurable. It includes an Ethernet Media Access Controller (MAC) with an Avalon® Streaming (Avalon-ST) interface on the client side, and a XAUI or a standard XGMII interface on the network side. The XAUI interface is implemented as hard IP in an Altera FPGA transceiver or as soft logic, which results in a soft 10GBASE-X XAUI PCS. Alternatively, you can choose to implement a 10-Gbps Ethernet IP core that includes only the MAC or the soft XAUI PCS.
This document serves as a design user guide for the Altera 10-Gbps Ethernet IP core, which implements the IEEE 802.3 2005 and 802.1Q Ethernet standards. It is categorized as a reference design and is highly configurable using the Quartus II MegaWizard GUI. The core includes an Ethernet Media Access Controller (MAC) with an Avalon Streaming interface and supports both hard IP and soft logic implementations for the XAUI physical coding sublayer (PCS).
The guide provides step-by-step instructions for the development flow, covering licensing options (including free time-limited evaluation via OpenCore Plus), downloading the library, parameterizing the IP core, functional verification using testbench files, and implementation steps such as placing constraints and performing timing analysis.
| Interface | Avalon Streaming (Avalon-ST) and XAUI |
|---|---|
| Throughput Rate | 10-Gbps full-duplex |
| FIFO Size | 64 bytes to 64 Kbytes |
| Maximum Frame Length | up to 64 KBytes |
| Standards Support | IEEE 802.3 2005 and 802.1Q |
You can use the Quartus II software to parameterize and implement this IP core in your design.
You can use the OpenCore Plus feature to temporarily try out the IP core for free using one of Altera's development boards.