This user guide introduces Altera Interlaken MegaCore Function, including function overview, configuration and usage instructions.
The Altera Interlaken MegaCore Function implements the Interlaken Protocol Specification, Revision 1.2, supporting high-speed serial communication for chip-to-chip packet transfers. It is designed for Stratix IV GT and Stratix IV GX devices, providing raw bandwidths ranging from 12.50 Gbps to 127.50 Gbps depending on the number of lanes and lane rates. Key features include compliance with the Interlaken Protocol Specification, support for 4 to 20 serial lanes, and the incorporation of a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.
| Protocol Specification | Interlaken Protocol Specification, Revision 1.2 |
|---|---|
| Supported Lanes | 4, 8, 10, 12, and 20 serial lanes |
| Per-lane Data Rates | 3.125, 6.25, 6.375, and 10.3125 Gbps |
| Raw Bandwidth | 12.50 Gbps to 127.50 Gbps |
| Device Support | Stratix IV GT and Stratix IV GX |
It implements the Interlaken Protocol Specification, Revision 1.2.
The function supports Stratix IV GT and Stratix IV GX device families.
The supported per-lane data rates are 3.125, 6.25, 6.375, and 10.3125 Gbps.