This article describes the features and characteristics of logic level and Snubberless TRIACs, and their current commutation capabilities when turned off.
The document explains that traditional TRIAC usage is limited by switching behavior risks, such as spurious triggering caused by high current or voltage slopes during turn-off. Designers typically mitigate these issues with over-rating, snubber networks, and temperature margins, which adds cost.
This note focuses on logic level and Snubberless TRIACs developed to offer high commutation capabilities without the need for external snubber circuits or complex interface requirements. It details the physics of turn-off, characterization methods involving critical di/dt versus dV/dt, application requirements for resistive and inductive loads, and the operational advantages of these advanced TRIAC technologies.
| Typical internal capacitance (1 A TRIAC) | 12 pF |
|---|---|
| Typical internal capacitance (12 A TRIAC) | 90 pF |
| Typical internal capacitance (24 A TRIAC) | 180 pF |
Standard TRIACs face a risk of spurious triggering after conduction if the slope of the decreasing current is too high or if the slope of the reapplied voltage is too high.
For Snubberless TRIACs, a minimum (dl/dt)c is specified without any (dV/dt)c limitation.
They allow for cost reduction by eliminating the need for an interface between the TRIAC gate and the logic circuit.