This document is an Engineer To Engineer Note from Analog Devices that provides a reference design for customers on how to interface a DRAM with the SHARC DSP using a DRAM Controller.
This document provides a reference design for customers on how to interface a DRAM with the SHARC DSP using a DRAM Controller implemented as a state-machine on a Xilinx PLD. The design has been simulated, built in hardware, and tested to operate successfully, though it has not been optimized for best performance.
The design utilizes a 4 Meg x 32 bit DRAM (MT8D432M-6x) manufactured by Micron and a 69 I/O pin Xilinx PLD (XC95108-10PC84). The controller handles page swapping and refreshing, using a refresh timer to generate requests every 15.525 µs. It supports CBR (CAS Before RAS) refresh methods and manages memory access requests during refresh cycles.
| DRAM Capacity | 4 Meg |
|---|---|
| DRAM Part Number | MT8D432M-6x |
| PLD Part Number | XC95108-10PC84 |
| Refresh Interval | 15.525 µs |
| Refresh Method | CBR |
| Clock Frequency | 40 Mhz |
It provides a reference design for customers on how to interface a DRAM with the SHARC DSP using a DRAM Controller.
The controller is implemented as a state-machine on a Xilinx PLD.
The design uses the CBR (CAS Before RAS) method for refreshing the DRAM.