This document introduces how Blackfin® processor emulates SPI interface through SPORT
The Blackfin family of embedded processors supports booting from SPI flash memory, but the native SPI interface is limited to a maximum clock rate of one-quarter the system clock. This document explains how to overcome this limitation by using the Serial Port (SPORT) interface, which can run at twice the speed of the standard SPI interface, to emulate an SPI connection for faster booting.
To achieve this, the document details the hardware configuration required to connect the SPORT pins to an SPI memory device, specifically addressing the lack of a native chip-select signal on the SPORT by utilizing frame sync signals. It further outlines the software process, which involves creating a Second Stage Loader (SSL) to take control after the initial boot ROM load, allowing the application to be booted via the faster SPORT interface.
| Maximum SPI clock rate (native) | one-quarter the system clock (ScLK) rate |
|---|---|
| Maximum SPI performance (native) | ~33 MHz |
| Maximum SPORT clock frequency | scLK/2 |
| Maximum SPI clock speed via SPORT emulation | ~66 MHz |
| Second Stage Loader size | 925 bytes |
No, the native Blackfin SPI interface is limited to a maximum clock rate of one-quarter the system clock, which translates to approximately 33 MHz if the system clock is 133 MHz.
By using one of the Blackfin serial ports (SPORTs) to emulate an SPI interface, as the maximum SPORT clock frequency is half the system clock (scLK/2).
No, SPORT booting is not supported by the Blackfin processor boot ROM, requiring specific hardware configuration and a secondary piece of software called a Second Stage Loader (SSL).