This document discusses the HD/CLI timing relationship in slave mode for the AD9929. The HD signal is used to reset internal counters and the timing relationship between HD and CLI is important for proper resetting. The document provides equations and ranges for the HD to CLI relationship for different SHDLOC values.
The document discusses the importance of the phase relationship between the external HD signal and the internal clock generated by CLI for the AD9929 device. It highlights that under specific timing conditions, the counter reset location can vary depending on temperature.
The note provides equations to calculate invalid regions for the time from the falling edge of HD to the rising edge of CLI (tuncu) based on the SHDLOC register value and a 36 MHz master clock. It includes a table specifying the minimum, typical, and maximum values for this timing relationship under standard operating conditions.
The HD signal is used to reset several internal counters.
The invalid values range from 18.8 ns to 24.8 ns.
The voltages must be between 2.7 V and 3.6 V.