This document provides notes on using Analog Devices' DSP, audio, and video components, focusing on the AD1849K's jitter requirements and input signal coupling.
This document, titled Engineer to Engineer EE-25, provides technical notes on using Analog Devices' DSP, audio, and video components from the Computer Products Division. It specifically addresses the AD1849K component, focusing on jitter requirements for external clock sources and the effects of AC versus DC signal coupling.
| Jitter Threshold | 2ns |
|---|---|
| THD Specification | -80dB |
| Sample Rate | 50kHz |
| Input Offset | less than 5mV |
Jitter should not exceed about 2ns to avoid raising the noise floor significantly above the system noise level.
Yes, crystal data for similar components indicates line inputs should be DC coupled for minimum output offset.