Describes the architecture of the ADV202 and its functional blocks, including data flow, interfaces and configuration methods.
This document provides an overview of the ADV202 architecture and its functional blocks. It details the embedded 32-bit RISC processor, wavelet transform engine, entropy codecs, and host interface capabilities. The note explains how the device handles data transfers between FIFOs and external DMA channels.
| Throughput | up to 65 MSPS |
|---|---|
| Wavelet Filters | 5/3 and 9/7 |
| Internal Memory | 500 kB |
| Processor | embedded 32-bit RISC processor |
The three entropy codecs can guarantee a throughput of up to 65 MSPS.
The device includes a wavelet transform engine with 5/3 and 9/7 wavelet filters.
There are 500 kB available for internal storage of wavelet data.