This paper describes how a Layer 2 Ethernet switch can be implemented using a low-cost, programmable logic-based architecture to meet specific requirements, increase integration, and enable highly customized solutions.
The document discusses the limitations of standard Application-Specific Switching Processors (ASSPs) for Layer 2 Ethernet switches, such as fixed port counts and speeds. It proposes a solution using Altera FPGAs and the Nios II embedded processor to create a customizable, single-chip switching engine.
The paper details the architecture of this programmable logic-based switch, highlighting its ability to support varying numbers of ports, non-standard speeds (e.g., 2-Gbps), and specific features like Quality of Service (QoS). It includes a case study on implementing a VoIP gateway using a Stratix II FPGA, providing resource utilization tables and performance data for different speed grades.
| Maximum switching capacity (latest high-density FPGAs) | 8 Gbps |
|---|---|
| MAC address table size | 2048 addresses |
| Embedded processor | 32-bit Nios II |
| QoS priority levels | eight levels |
| Switching operation mode | non-blocking |
| Device Speed Grade 3 Maximum Clock Frequency | 260 MHz |
| Device Speed Grade 3 Switching Capacity | 8 Gbps |
| Total Logic Elements (LEs) Utilization (VoIP Gateway Example) | 14,700 |
| Total Memory Bits Utilization (VoIP Gateway Example) | 366K |
The embedded processor manages table management tasks such as learning, aging, and migration, as well as high-level functions like spanning tree algorithms and Ethernet termination.
The switch classifies frames based on header information into up to eight priority levels and stores them in high and low priority queues, using strict priority or weighted round-robin arbitration.