TDA1305T is a stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2). It features easy application, selectable system clock, digital filters, smooth transitions before and after muting, digital de-emphasis filter, and other characteristics.
The TDA1305T is an integrated circuit featuring a unique combination of bitstream and continuous calibration techniques. It functions as a bitstream converter for low signals while using dynamic continuous calibration for large signals, resulting in low power consumption and small chip size.
The device incorporates a 16th-order Finite-duration Impulse-Response (FIR) filter and a 2nd order noise shaper. It supports selectable system clock frequencies of 256fs or 384fs with various serial input formats, including 2S-bus and LSB fixed modes. The chip includes two on-board operational amplifiers to convert digital-to-analog current to output voltage.
| Digital supply voltage (VDDP) | 3.4 to 5.5 V |
|---|---|
| Analog supply voltage (VDDA) | 3.4 to 5.5 V |
| Full-scale output voltage (VFSM) | 1.5 V RMS |
| Total harmonic distortion plus noise (THD+N) | -90 dB |
| Signal-to-noise ratio (S/N) A-weighted | 100 to 108 dB |
| Operating ambient temperature (Tamb) | -30 to +85 °C |
| System clock frequency range | 6.4 to 18.432 MHz |
The maximum input bit rate at data input in normal speed mode is 3.072 Mbits when fs = 48 kHz.
The maximum input bit rate in double speed mode is 6.144 Mbits when fs = 48 kHz.
No, no analog post filtering is required because the device incorporates a sample-and-hold function and noise shaper.