This is a datasheet for DM74174 Hex/Quad D-Type Flip-Flop with Clear. The flip-flops utilize TTL circuitry to implement D-type flip-flop logic and have a direct clear input. Information at the D inputs meeting the setup and hold time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or LOW level, the D input signal has no effect at the output. The product contains six flip-flops with single-rail outputs and features buffered clock and direct clear inputs.
This document is a technical datasheet for the Fairchild Semiconductor DM74174 integrated circuit. It describes a positive-edge triggered flip-flop utilizing TTL circuitry that features single-rail outputs, buffered clock inputs, and direct clear inputs. The device contains six flip-flops suitable for applications such as buffer/storage registers, shift registers, and pattern generators.
| Number of Flip-Flops | Six |
|---|---|
| Typical Clock Frequency | 40 MHz |
| Typical Power Dissipation per Flip-Flop | 38 mW |
| Package Description | 16-Lead Plastic Dual-In-Line Package (PDIP) |
| Maximum Clock Frequency | 30 MHz |
Yes, all flip-flops in the DM74174 utilize TTL circuitry to implement D-type logic with a direct clear input.
The maximum clock frequency is 40 MHz under typical conditions and 30 MHz under recommended operating conditions.