This document is the technical specification of Motorola MC68306. It introduces the features and characteristics of the product.
The Motorola MC68306 is an integrated processor designed to reduce design time, component count, power consumption, board space, and cost. It combines the functionality of the MC68EC000 microprocessor with various system elements common in 68000-based systems into a single chip.
Key features include complete code compatibility with the MC68000 and MC68EC000, high performance at 2.4 MIPS, two-channel universal synchronous/asynchronous receiver/transmitters (DUART), an integrated 16-bit timer/counter, and a dynamic random access memory (DRAM) controller supporting up to 64 Mbytes.
| Performance | 2.4 MIPS |
|---|---|
| Clock Frequency | 16.67-MHz, 5-V Operation |
| Address Lines | 24 Address Lines |
| Data Lines | 16 Data Lines |
| DRAM Support (Max) | 64 Mbytes using 16M x 1 DRAMs |
| Package Types | 128-Pin Plastic Quad Flat Pack (QFP) or 132-Pin Plastic Quad Flat Pack (PQFP) |
It reduces design time by providing valuable system elements pre-packaged in one chip.
Yes, it affords access to a broad base of established real-time kernels and operating systems due to complete code compatibility.
It includes two-channel serial I/O ports, an interrupt controller, a DRAM controller, chip selects, a bus watchdog timer, and a 16-bit timer.