The TigerSHARC® Embedded Processor ADSP-TS203S Rev. PrB is a high-performance static superscalar DSP processor with a 500 MHz, 2.0 ns instruction cycle rate, 4M bits of internal DRAM memory and a 25×25 mm (576-ball) thermally enhanced ball grid array package.
The ADSP-TS203S is an ultra-high performance, static superscalar processor optimized for large signal processing tasks and communications infrastructure. It combines very wide memory widths with dual computation blocks to support 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing.
Operating at 500 MHz, the processor's core has a 2.0 ns instruction cycle time. Using its Single-Instruction, Multiple-Data (SIMD) features, it can perform four billion 40-bit MACs or one billion 80-bit MACs per second.
| Operating Frequency | 500 MHz |
|---|---|
| Instruction Cycle Time | 2.0 ns |
| Internal Memory Size | 4M Bits |
| Internal Memory Bandwidth | 28 Gbytes per second |
The processor achieves one billion MACs/s peak performance.
The external port supports a 1/0 DMA Transfer Rate of 500M bytes/s.
Yes, the ADSP-TS203S processor is code-compatible with the other TigerSHARC processors.