Analog Devices ADSP-2196 DSP Microcomputer Preliminary Technical Data Sheet

About this manual

This document provides preliminary technical data for the ADSP-2196 DSP Microcomputer. Key features include a 6.25 ns instruction cycle time supporting up to 160 MIPS sustained performance, dual-purpose program memory, and fully transparent instruction cache allowing dual operand fetches in every cycle.

The device includes 16K words of on-chip RAM (configured as 8K words 24-bit and 8K words 16-bit) and 16K words of on-chip 24-bit ROM. It features three full-duplex multichannel serial ports supporting H.100 standards, two SPI-compatible ports with DMA capability, and one UART port. The chip operates at 2.5 V internally with 3.3 V compliant I/O and is available in 144-lead LQFP and Mini-BGA packages.

What's inside

• ADSP-2196 DSP Core Features
• Functional Block Diagram
• Internal (On-Chip) Memory
• External (Off-Chip) Memory
• Interrupts and DMA Controller
• Host Port
• DSP Serial Ports (SPORTs)
• Low Power Operation
• Electrical Characteristics
• Pin Descriptions

Specifications

Frequently asked questions

What is the maximum sustained performance of the ADSP-2196?

The device supports up to 160 MIPS sustained performance.

What is the size and configuration of the on-chip RAM?

It contains 16K words configured as 8K words of 24-bit RAM and 8K words of 16-bit RAM.

What is the instruction cycle time for internal operations?

The internal instruction cycle time is 6.25 ns.