Update: 29 September, 2023
The SY87700V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 175Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87700V also includes a link fault detection circuit.
File format: PDF
Size: -
MD5 Checksum: 6A002A94A52D89286C242431FCCBA30D
Publication date: 08 June, 2012
Downloads: -
PDF Link: MICREL SY87700V handbook PDF