Micrel KS8995XA Integrated 5-Port 10/100 QoS Switch Datasheet

The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch with optimized bill of materials (BOM) cost for low port count, cost-sensitive 10/100Mbps switch systems. It also provides an extensive feature set including three different QoS priority schemes, a dual MII interface for BOM cost reduction, rate limiting to offload CPU tasks, software and hardware power-down, a MDC/MDIO control interface and port mirroring/monitoring to effectively address both current and emerging Fast Ethernet applications. The KS8995XA contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. All PHY units support 10BASE-T and 100BASE-TX. In addition, two of the PHY units support 100BaseFX (Ports 4 and 5).


Micrel KS8995XA Integrated 5-Port 10/100 QoS Switch Datasheet - cover page
Brand
Micrel
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
51
File format
PDF
File size
282 KB
Published
01 August, 2012
Updated
28 September, 2023
MD5 checksum
2AD6FB3512E2D4BE5C207DDA0CD6E268

About this manual

The KS8995XA is a highly integrated Layer-2 quality of service (QoS) switch designed for cost-sensitive 10/100Mbps systems. It contains five 10/100 transceivers with patented mixed-signal low-power technology, five media access control (MAC) units, and a high-speed non-blocking switch fabric.

The device supports three different QoS priority schemes, rate limiting to offload CPU tasks, and software/hardware power-down capabilities. It features dual MII interfaces for BOM cost reduction and includes an on-chip frame buffer memory of 64Kbytes.

What's inside

  • General Description
  • Features
  • Applications
  • Ordering Information
  • Functional Overview
  • Switch Core Operation
  • Configuration Interface
  • Register Map
  • Electrical Characteristics
  • Timing Diagrams

Specifications

Number of PortsFive 10/100 transceivers
Switch Fabric TypeShared memory based non-blocking
Frame Buffer Memory64Kbyte
Memory Bandwidth1.4Gbps
MAC Address Table Size1K unicast addresses
Operating Temperature Range0°C to +70°C
Package Type128-pin PQFP

Frequently asked questions

What are the supported Ethernet speeds?

All PHY units support 10BASE-T and 100BASE-TX, with two PHY units also supporting 100BaseFX.

Does the switch support VLANs?

Yes, it supports VLAN ID tag/untag options on a per-port basis and port-based VLAN support.

What is the core voltage?

The core operates at 1.8V.

Download PDF (282 KB)

More Micrel Manuals


View all Micrel manuals →