The M54/74HCT373 and M54/74HCT533 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C2MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. These 8 bit D-Type latches are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while high level the outpts will be in a high impedance state. The application designer has a choise of combination of inverting and non inverting.
This document describes the M54/74HCT373 (non-inverting) and M54/74HCT533 (inverting) high-speed CMOS octal D-type latches with 3-state outputs. Fabricated using silicon gate CMOS technology, these integrated circuits achieve high speed operation similar to LSTTL while maintaining low power dissipation.
| Propagation Delay (Typical) | 17 ns |
|---|---|
| Power Dissipation (Max) | 4 mW |
| Supply Voltage Range | 4.5 to 5.5 V |
| Operating Temperature (M74HC Series) | -40 to +85 °C |
| Input High Voltage (Min) | 2.0 V |
The HCT373 has non-inverting outputs, while the HCT533 has inverting outputs.
Yes, they are fully compatible with 54/74 LSTTL logic families.
The minimum input voltage (Vin) for a high level is 2.0 V.