Describes the Interfacing between the AMD-761 TM System Controller and the Via Technologies, Inc. VT82C686B Southbridge
This document addresses two specific incompatibilities that occur when creating a system design using the AMD-761 System Controller (Northbridge) and the Via Technologies, Inc. VT82C686B Southbridge. The first issue involves the Write Snoop Complete (WSC#) protocol, which mandates an alternative configuration to ensure proper function and compliance with the Microsoft PC-2001 specification. The second issue concerns potential data corruption when switching into the ACPI S3 power management state in systems utilizing registered DDR DIMMs due to incompatible sequencing of the PCIRESET# pin.
The document provides detailed background information on these incompatibilities and offers specific hardware solutions. For the WSC# protocol, it recommends connecting the signal through an unpopulated resistor pad to allow for POP/NOPOP capability. For the ACPI S3 state issue, it explains the required sequencing of the DCSTOP# and PCIRESET# pins to prevent data corruption when entering or exiting the suspend state.
This document describes two system-level incompatibilities that occur when creating a system with the AMD-761 system controller and the Via Technologies, Inc. VT82C686B southbridge.