The BU1923 and BU1923F are RDS / RBDS decoders that employ a digital PLL and have a built-in anti-aliasing filter and an eight-stage BPF (switched-capacitor filter). Linear CMOS circuitry is used for low power consumption.
The BU1923 and BU1923F are RDS/RBDS decoder ICs designed for FM receivers, car stereos, high‑fidelity systems and FM pagers. They use linear CMOS circuitry for low power consumption and operate at 5 V supply.
Key features include low current draw, a two‑stage anti‑aliasing filter, a 57 kHz eight‑stage band‑pass filter, digital PLL demodulation, and a quality‑indication output. Electrical specifications such as clock frequency (1187.5 Hz) and data timing (valid for 416.7 µs) are provided, along with pin descriptions and external dimensions.
| Current consumption | Low |
|---|---|
| Anti‑aliasing filter | Two‑stage LPF |
| Band‑pass filter | 57 kHz |
| Demodulation method | DSB digital PLL |
| Quality output | HI/LO |
| RCLK clock frequency | 1187.5 Hz |
| Data valid time | 416.7 µs |
| Supply voltage VDD | 5.0 V |
| Ground voltage VSS | 0.0 V |
The RCLK clock runs at 1187.5 Hz.
Data can be sampled on either the rising or falling edge of the clock and is valid for 416.7 µs after the reference edge.