The L67132 and L67142 are low‑power 2 K × 8 CMOS dual‑port static RAMs that can be used as standalone 8‑bit devices or combined in a master/slave configuration to form wider data buses. Each port has independent address, control and I/O pins, an automatic power‑down feature, and on‑chip arbitration that resolves contention and asserts a BUSY flag on the inhibited port.
The document provides detailed pin‑out diagrams for 48‑pin DIL, 52‑pin PLCC, 48‑pin LCC and 64‑pin VQFP packages, electrical characteristics such as supply voltage, standby current and battery‑backup operation, and timing parameters for read and write cycles. It also lists ordering information and applicable military and space qualification standards.
| Memory organization | 2048 × 8 bits |
|---|---|
| Typical standby supply current | 1 µA (typ) |
| Battery backup retention voltage | 2 V |
| Access time | 45 ns to 70 ns |
On‑chip arbitration logic resolves address or chip‑select matches within about 5 ns and asserts a BUSY flag on the inhibited port.
Yes, it provides data retention with a 2 V backup voltage when chip‑select is held high.