TEMIC TS80C31X2 is a high-performance CMOS and ROMless version of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C31X2 retains all features of the TEMIC TSC80C31 with 128 bytes of internal RAM, a 5-source, 4 priority level interrupt system, an on-chip oscillator, and two timer/counters. In addition, the TS80C31X2 has a dual data pointer, a more versatile serial channel that facilitates multiprocessor communication (EUART), and an X2 speed improvement mechanism. The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C31X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode, the CPU is frozen while the timers, the serial port, and the interrupt system are still operating. In the power-down mode, the RAM is saved and all other functions are inoperative.
The TEMIC TS80C31X2 is a high-performance 8-bit CMOS microcontroller designed as a ROMless version of the 80C51 single-chip architecture. It retains key features such as 128 bytes of internal RAM, a 5-source interrupt system, and an on-chip oscillator, while adding a dual data pointer and a versatile serial channel for multiprocessor communication.
The device offers a high-speed architecture with an X2 speed improvement mechanism, allowing operation at up to 60 MHz at 5V. It includes power control modes for reduced activity, a full-duplex enhanced UART with framing error detection, and compatibility with 80C31 pin and instruction sets. The microcontroller is available in various packages including PDIL40, PLCC44, and VQFP44.
| Architecture | 8-bit CMOS |
|---|---|
| Clock Frequency | 0-60 MHz |
| Internal RAM | 128 bytes |
| Interrupt Sources | 5 |
| Timer/Counters | Two 16-bit |
| Power Supply (Commercial) | 4.5-5.5V |
| Operating Temperature (Commercial) | 0 to 70°C |
| Operating Temperature (Industrial) | -40 to 85°C |
| Packages | PDIL40, PLCC44, VQFP44, PQFP44 |
The X2 feature allows the core to need only 6 clock periods per machine cycle instead of 12, effectively doubling the CPU speed or allowing the use of cheaper crystals.
The device has two software-selectable modes: Idle mode, where the CPU is frozen but peripherals operate, and Power-down mode, where all functions are inoperative.