IDT IDT5T9310 2.5V LVDS 1:10 Clock Buffer Terabuffer™ II Datasheet

IDT5T9310 is a 2.5V LVDS 1:10 clock buffer from IDT


IDT IDT5T9310 2.5V LVDS 1:10 Clock Buffer Terabuffer™ II Datasheet - cover page
Brand
IDT
Category
Clocks and Timers
Document type
Datasheet
Language
English
Pages
13
File format
PDF
File size
94 KB
Published
10 May, 2012
Updated
30 September, 2023
MD5 checksum
FA447FE7704AB3B6514CBBCF3F92B3B2

About this manual

The IDT5T9310 is a 2.5 V LVDS 1:10 clock buffer designed for clock distribution in high‑speed systems. It offers guaranteed low skew (< 25 ps), very low duty‑cycle distortion (< 125 ps), and propagation delay under 1.75 ns, supporting up to 1 GHz operation. The device accepts a wide range of input standards (LVTTL, HSTL, eHSTL, LVEPECL, LVPECL, CML, LVDS) and provides ten selectable LVDS outputs, with hot‑insertable and over‑voltage tolerant inputs.

The datasheet details electrical characteristics, pin configuration, absolute maximum ratings, and recommended operating conditions. It specifies power‑supply voltage ranges, input and output voltage limits, and timing parameters such as skew and propagation delay. Ordering information and package details (VFQFPN) are also provided.

What's inside

  • Features
  • Applications
  • Pin Configuration
  • Absolute Maximum Ratings
  • Electrical Characteristics
  • Differential Input AC Test Conditions
  • Power Supply Characteristics
  • Ordering Information

Specifications

Maximum Skew< 25 ps
Duty‑Cycle Distortion< 125 ps
Propagation Delay< 1.75 ns
Maximum Operating Frequency1 GHz
Power‑Supply Voltage (VDD)0.5 V to 3.6 V
Operating Temperature Range-40 °C to +85 °C
PackageVFQFPN
Number of LVDS Outputs10

Frequently asked questions

What is the maximum skew of the IDT5T9310?

The device guarantees a maximum skew of less than 25 ps.

What is the highest frequency the IDT5T9310 can operate at?

It can operate up to 1 GHz.

How many LVDS outputs does the IDT5T9310 provide?

It provides ten LVDS outputs.

What should be done before powering down the device?

Outputs should be disabled before entering power‑down mode.

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