Update: 30 September, 2023
This document is the product manual of IDT71V2556/58 3.3V high-speed synchronous SRAM devices. It introduces the features and characteristics of the devices, including 128K x 36, 256K x 18 memory configurations, 200 MHz high performance system clock speed, ZBTTM feature, single R/W control pin, 4-word burst capability, individual byte write control, three chip enables, 3.3V power supply, 2.5V I/O supply, JEDEC standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA).
File format: PDF
Size: -
MD5 Checksum: 30F8352C7AC030A91844FDAA0E3086C5
Publication date: 10 May, 2012
Downloads: -
PDF Link: IDT IDT71V2556S/IDT71V2558S/IDT71V2556SA/IDT71V2558SA Manual PDF