This document describes the features and characteristics of the Advanced Micro Devices PALCE20V8 Family EE CMOS 24-Pin Universal Programmable Array Logic, including pin and function compatibility with all GAL 20V8/As, electrically erasable CMOS technology, high-speed CMOS technology, direct plug-in replacement for a wide range of 24-pin PAL devices, programmable enable/disable control, individually programmable outputs as registered or combinatorial, Peripheral Component Interconnect (PCI) compliance, preloadable output registers for testability, automatic register reset on power-up, cost-effective 24-pin plastic SKINNYDIP and 28-pin PLCC packages, extensive third-party software and programmer support, fully tested for 100% programming and functional yields and high reliability, and programmable output polarity.
The PALCE20V8 is an advanced, electrically‑erasable CMOS programmable array logic (PAL) device from AMD. It offers eight configurable macrocells, selectable as registered or combinatorial outputs, and supports both commercial and industrial temperature ranges. The device is pin‑compatible with GAL20V8 and can replace a wide range of 24‑pin PAL parts.
The datasheet provides detailed functional descriptions, macrocell configuration options, pin designations, package information, power‑up reset behavior, programming and erasing procedures, as well as compliance with PCI specifications. It also outlines security features such as a programmable security bit and an electronic signature word.
| Propagation delay (‑5 version) | 5 ns |
|---|---|
| Propagation delay (‑7 version) | 7.5 ns |
| Package types | 24‑Pin 300 mil Plastic (SKINNYDIP) and 28‑Pin PLCC |
| Power‑Up Reset Time | 1000 ns |
| Operating temperature ranges | Commercial 0 °C to +75 °C; Industrial –40 °C to +85 °C |
The PALCE20V8 has a 5 ns propagation delay for the “‑5” version and a 7.5 ns delay for the “‑7” version.
It is available in a 24‑pin 300 mil plastic SKINNYDIP package and a 28‑pin PLCC package.