ANALOG DEVICES SigmaDSP 28-/56-Bit Audio Processor with Two ADCs Four DACs ADAU1701 handbook

SigmaDSP® 28-/56-Bit Audio Processor with Two ADCs and Four DACs. Features include complete standalone operation, self-boot from serial EEPROM, auxiliary ADC with 4-input mux for analog control, GPIOs for digital controls and outputs, fully programmable with SigmaStudio™ graphical tool, etc.


ANALOG DEVICES SigmaDSP 28-/56-Bit Audio Processor with Two ADCs Four DACs ADAU1701 handbook - cover page
Brand
Analog Devices
Category
Audio Codec
Document type
User Manual
Language
English
Pages
52
File format
PDF
File size
1.1 MB
Published
08 May, 2012
Updated
29 September, 2023
MD5 checksum
78216737710B7046C3044CCE3BC77E77

About this manual

The ADAU1701 is a single‑chip audio system that combines a 28‑/56‑bit SigmaDSP® audio processor, two high‑performance ADCs, four DACs, and a microcontroller‑like control interface. It supports full‑precision 56‑bit processing, flexible serial data ports, and can be programmed with the SigmaStudio™ graphical tool.

The handbook details functional block diagrams, electrical specifications, timing requirements, and register maps, enabling designers to integrate the device into multimedia speakers, automotive head units, digital TVs, and other audio applications.

What's inside

  • Features
  • Applications
  • Specifications
  • Digital Input/Output
  • Power
  • Temperature Range
  • PLL and Oscillator
  • Digital Timing Specifications
  • Absolute Maximum Ratings

Specifications

ADC Signal‑to‑Noise Ratio (A‑Weighted)100 dB
DAC Signal‑to‑Noise Ratio (A‑Weighted)104 dB
ADC Total Harmonic Distortion + Noise-83 dB
DAC Total Harmonic Distortion + Noise-90 dB
Number of ADC channels2
Number of DAC channels4
Maximum sampling rate192 kHz
PLL lock time20 ms

Frequently asked questions

What is the maximum sampling rate supported by the ADAU1701?

The device supports sampling rates up to 192 kHz.

How many ADCs does the ADAU1701 have?

The ADAU1701 includes two ADCs.

What is the PLL lock time of the ADAU1701?

The PLL lock time is specified as 20 ms.

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