The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip−flop. The J/K data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation.
The MC10/100EP35 devices are higher‑speed, low‑voltage versions of the EL35 JK flip‑flop. Data is entered on the master side when the clock is low and transferred to the slave on a rising clock edge; the asynchronous reset is active high. The 100 series adds temperature compensation and supports both PECL and NECL modes.
Key specifications include a 410 ps propagation delay, >3 GHz maximum frequency, supply current 30‑50 mA, and a range of package options (SOIC‑8, TSSOP‑8, DFN‑8). The datasheet provides pin descriptions, truth tables, maximum ratings, DC and AC characteristics, typical termination diagrams, and full ordering information.
| Propagation Delay | 410 ps |
|---|---|
| Maximum Frequency | > 3 GHz |
| PECL Mode Supply Voltage Range | VCC = 3.0 V to 5.5 V, VEE = 0 V |
| NECL Mode Supply Voltage Range | VCC = 0 V, VEE = –3.0 V to –5.5 V |
The device has a propagation delay of 410 ps.
They can operate at frequencies greater than 3 GHz.
PECL mode works with VCC from 3.0 V to 5.5 V while VEE is 0 V.
The SOIC‑8 package has eight pins.