Texas Instruments SN54AC374 / SN74AC374 Octal D-Type Edge-Triggered Flip-Flops Datasheet

This document describes an 8-bit flip-flop with 3-state outputs, designed for driving highly capacitive or relatively low-impedance loads. The product is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.


Texas Instruments SN54AC374 / SN74AC374 Octal D-Type Edge-Triggered Flip-Flops Datasheet - cover page
Brand
Texas Instruments
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
18
File format
PDF
File size
716 KB
Published
08 May, 2012
Updated
28 September, 2023
MD5 checksum
09E94A3F30D1368044E6A42C6D361EDC

About this manual

The SN54AC374 and SN74AC374 are 8‑bit, edge‑triggered D‑type flip‑flops with three‑state outputs. They are intended for use as buffers, I/O ports, bidirectional bus drivers, and working registers in bus‑organized systems, allowing high‑impedance states without external pull‑up components.

Key electrical characteristics include a supply voltage range of 2 V to 6 V, propagation delays as low as 9.5 ns at 5 V, continuous output currents up to 50 mA, and maximum clock frequencies up to 100 MHz. The datasheet also lists detailed package information, thermal impedance values, and recommended operating conditions.

What's inside

  • Description / Ordering Information
  • Function Table
  • Recommended Operating Conditions
  • Electrical Characteristics
  • Timing Requirements
  • Switching Characteristics
  • Parameter Measurement Information
  • Package Option Addendum
  • Mechanical Data
  • Important Notice

Specifications

Supply voltage (VCC)2 V – 6 V
Maximum propagation delay (tpg)9.5 ns at 5 V
Continuous output currentup to 50 mA
Maximum clock frequencyup to 100 MHz
Hold time (tH)1 ns
Package thermal impedance (DB)70 °C/W

Frequently asked questions

What is the supply voltage range for the SN54AC374 / SN74AC374?

The devices operate with a supply voltage (VCC) from 2 V to 6 V.

What is the maximum clock frequency of these flip‑flops?

The maximum clock frequency is up to 100 MHz, depending on the specific package.

How many pins does the PDIP package have?

The PDIP version of the device has 16 pins.

How should the OE pin be handled during power‑up or power‑down?

OE should be tied to VCC through a pull‑up resistor; the minimum resistor value is set by the driver’s current‑sinking capability.

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