The MAX5856A dual, 8-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5856A integrates two 8-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock multiplier, and a 1.24V reference. The MAX5856A supports single-ended and differential modes of operation. The MAX5856A dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of -1.0V to +1.25V. The 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. The PLL multiplier generates all internal synchronized high-speed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5856A to be updated on a single 8-bit bus. The MAX5856A features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustment.
The MAX5856A dual‑channel DAC from Maxim provides 8‑bit resolution and a maximum update rate of 300 Msps. It integrates programmable 4×/2×/1× interpolation filters and an internal PLL multiplier, supporting both single‑ended and differential outputs over a 2.7 V to 3.3 V supply range. The device offers full‑scale output currents from 2 mA to 20 mA and complies with a –1.0 V to +1.25 V output voltage range.
The part is supplied in a 48‑pin TQFP‑EP package rated for –40 °C to +85 °C operation. Detailed electrical characteristics, absolute maximum ratings, and typical performance graphs are provided, including a spurious‑free dynamic range of 68 dBc at 20 MHz and low‑power standby modes with 1 pA quiescent current.
| Resolution | 8 bits |
|---|---|
| Maximum DAC Update Rate | 300 Msps |
| Package | 48‑pin TQFP‑EP |
| Operating Temperature Range | -40 °C to +85 °C |
| Spurious‑Free Dynamic Range (SFDR) | 68 dBc at 20 MHz |
The DAC is supplied in a 48‑pin TQFP‑EP package with an exposed paddle for thermal dissipation.
The device achieves an SFDR of 68 dBc at a 20 MHz output frequency.