The MAX5877 is an advanced 14-bit, 250Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 75dBc spurious-free dynamic range (SFDR) at fOUT = 16MHz and supports update rates of 250Msps, with a power dissipation of only 287mW. The MAX5877 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1VP-P to 1VP-P differential output voltage swing. The device features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy. The clock inputs of the MAX5877 accept both LVDS and LVPECL-compatible voltage levels. The device features an interleaved data input that allows a single LVDS bus to support both DACs. The MAX5877 is available in a 68-pin QFN package with an exposed pad (EP) and is specified for the extended temperature range (-40°C to +85°C). Refer to the MAX5876 and MAX5878 data sheets for pin-compatible 12-bit and 16-bit versions of the MAX5877, respectively. Refer to the MAX5874 data sheet for a CMOS-compatible version of the MAX5877.
The MAX5877 is a 14‑bit, 250 Msps dual digital‑to‑analog converter designed for high‑dynamic‑performance applications such as wireless base stations, DDS, and test equipment. It operates from +3.3 V and +1.8 V supplies and offers a full‑scale output current of 2 mA to 20 mA with a differential voltage swing of 0.1 V‑1 V.
The datasheet details absolute maximum ratings, electrical characteristics, pin functions, and typical operating curves. It includes power‑dissipation figures, noise spectral density, spurious‑free dynamic range, and package information for the 68‑pin QFN‑EP device.
| Resolution | 14 Bits |
|---|---|
| Output Update Rate | 250 Msps |
| Analog Supply Voltage (AVDD3.3) | 3.135 V – 3.465 V |
| Noise Spectral Density | -160 dBFS/Hz at 16 MHz |
| Spurious‑Free Dynamic Range (SFDR) | 75 dBc at 16 MHz |
AVDD3.3 accepts 3.135 V to 3.465 V and AVDD1.8 accepts 1.71 V to 1.89 V.
It is supplied in a 68‑pin QFN‑EP package.