MAX9691/MAX9692/MAX9693 are ultra-fast ECL comparators capable of very short propagation delays. Their design maintains the excellent DC matching characteristics normally found only in slower comparators. MAX9691/MAX9692/MAX9693 have differential inputs and complementary outputs that are fully compatible with ECL-logic levels. Output current levels are capable of driving 50Ω terminated transmission lines. The ultra-fast operation makes signal processing possible at frequencies in excess of 600MHz. MAX9692/MAX9693 feature a latch-enable (LE) function that allows the comparator to be used in a sample-hold mode. When LE is ECL high, the comparator functions normally. When LE is driven ECL low, the outputs are forced to an unambiguous ECL-logic state, dependent on the input conditions at the time of the latch input transition. If the latch-enable function is not used on either of the two comparators, the appropriate LE input must be connected to ground; the companion LE input must be connected to a high ECL logic level. These devices are available in SO, QSOP, and tiny µMAX® packages for added space savings.
The MAX9691, MAX9692, and MAX9693 are ultra‑fast ECL comparators featuring differential inputs, complementary outputs, and latch‑enable functionality for sample‑hold operation. They can drive 50 Ω terminated transmission lines and operate at frequencies above 600 MHz.
Key specifications include propagation delays of 1.2 ns (typical), 100 ps skew, 150 ps dispersion, and latch‑enable setup and pulse‑width times of 0.5 ns. The devices are offered in µMAX, SO, QSOP, and PDIP packages and require +5 V and –5.2 V supplies. Recommended layout practices emphasize a solid ground plane and proper decoupling for high‑speed performance.
| Latch‑Enable Setup Time | 0.5 ns |
|---|---|
| Latch‑Enable Pulse Width | 0.5 ns |
| Supply Voltage Range | +5 V to –5.2 V |
The latch‑enable function allows the comparator to operate in a sample‑hold mode; when LE is high the comparator works normally, and when LE is low the outputs are forced to a defined ECL‑logic state.
A solid ground plane, close‑by 0.01 µF decoupling capacitors, and microstrip routing with 50 Ω termination are required for optimal high‑speed performance.