This document introduces three M2S28D series DDR SDRAM products: M2S28D20ATP, M2S28D30ATP, and M2S28D40ATP. These products adopt double data rate synchronous DRAM architecture, with high-speed data transfer capability, suitable for main memory in computer systems. The products feature double data rate architecture, bidirectional data strobe transmission, differential clock inputs, and auto precharge, etc.
The handbook describes the M2S28D20, M2S28D30 and M2S28D40ATP DDR SDRAM parts, each offering 128 Mbit density in a 66‑pin TSOP package. It outlines the double‑data‑rate architecture, voltage requirements, timing parameters, and programmable features such as CAS latency, burst length and burst type.
Detailed sections cover pin‑out diagrams, signal definitions, command truth tables, function truth tables, power‑down modes, and data‑mask control. Safety and disclaimer information are also included to guide designers in reliable circuit implementation.
| Supply Voltage | Vdd = Vddq = 2.5 V ±0.2 V |
|---|---|
| Maximum Data Rate | 133 MHz |
| Density | 128 Mbit |
| CAS Latency | 2.0 / 2.5 (programmable) |
| Burst Length | 2 / 4 / 8 (programmable) |
| Interface | SSTL‑2 |
The device uses Vdd = Vddq = 2.5 V ±0.2 V.
They can operate up to 133 MHz.
The SDRAM uses an SSTL‑2 interface.