This document is a user manual for Z80 CPU peripherals, describing the features and characteristics of Z80 CPU peripherals.
This manual provides a complete description of the Z80 CPU peripheral family, covering counter/timer channels, direct memory access, serial I/O, parallel I/O, and related control logic. It includes architecture overviews, register descriptions, programming modes, and timing diagrams for each peripheral block.
Detailed sections explain interrupt daisy‑chain operation, RETI handling, and nested interrupt servicing, as well as pin assignments for various PLCC packages. The document serves engineers and developers who need to integrate or program Z80 peripheral chips in their designs.